Chip package having a patterned conducting plate and a conducting pad with a recess
US10074581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2016 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.