Integrated semiconductor device having isolation structure for reducing noise
US10074644B2 · kind B2 · utility
4Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.