Fin semiconductor device including dummy gate on isolation layer
US10074726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2015 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | May 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
Abstract
A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a first direction, a first device isolation region disposed at a sidewall of the active fin and extending in a second direction, the second direction crossing the first direction, a normal gate electrode crossing the active fin, a first dummy gate electrode having an undercut portion on the first device isolation region, the first dummy gate electrode extending in the second direction, and a first filler filling the undercut portion on the first device isolation region, wherein the undercut portion is disposed at a lower portion of the first dummy gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.