Continuous time linear equalizer with two adaptive zero frequency locations
US10075141B1 · kind B1 · utility
9Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03535
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.