Phase noise measurement and filtering circuit
US10075145B2 · kind B2 · utility
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8References
6Claims
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Key dates
| Filing date | May 25, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | May 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.