Set-reset latches
US10075150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2016 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.