Integrated circuit with multiplexed pin and pin multiplexing method
US10075152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Sep 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit with a multiplexed pin and a pin multiplexing method. The multiplexed pin of the integrated circuit extends out with two connecting ends to receive two logic level signals which are finally restored in a chip. A first signal input end receives a signal representing whether to enable or disable, a second signal input end receives a function signal which achieves a certain function, and a diode, a resistor, and a first current source are used together to achieve multiplexing of the pin based on turn-on and clamping characteristics of the diode. The number of pins to be packaged and the area occupied by a chip on board are reduced, which is conducive to a small package design of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.