Low-power clock-gated synchronizer, a data processing system that incorporates the same and a synchronization method
US10075153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Dec 27, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.