ΔΣ modulator with excess loop delay compensation
US10075181B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/428
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.