System for identifying a 3D chip
US10075694B2 · kind B2 · utility
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2References
25Claims
0Family size
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Key dates
| Filing date | Aug 18, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54473
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.