Wafer level integrated circuit probe array and method of construction
US10078101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.