Processing denormal numbers in FMA hardware
US10078512B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2016 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Jan 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp+Bexp−Cexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to −K (where K is related to a width of a datapath in the partial product adder), and when a C is denormal and its number of leading zeroes plus K exceeds −ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.