Memory system, error correction device, and error correction method
US10078550B2 · kind B2 · utility
1Cited by
8References
9Claims
0Family size
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Key dates
| Filing date | Sep 1, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.