Multiple-core computer processor for reverse time migration

US10078593B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• John Shalf · Oakland, US
• David Donofrio · San Francisco, US
• Leonid Oliker · San Francisco, US
• Jens KRÜGER · Ravensburg, DE
• Samuel John Williams · Lenoir City, US

Key dates

• Filing date: Oct 26, 2012
• Grant date: Sep 18, 2018
• Expiry date: Aug 4, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.