Computing in parallel processing environments
US10078613B1 · kind B1 · utility
19Cited by
5References
34Claims
0Family size
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Inventor
Key dates
| Filing date | Mar 3, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Oct 16, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.