Runtime reconfigurable dataflow processor with multi-port memory access module
US10078620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2012 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Sep 12, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perforin a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.