Structure for isolating high speed digital signals in a high density grid array
US10079202B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | May 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0207
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use “single-ended” (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.