Vertical memory devices and methods of manufacturing the same
US10079203B2 · kind B2 · utility
2Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2016 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.