Calibrated lookup table for phase-locked loop reconfiguration
US10079607B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.