DAC capacitor array, analog-to-digital converter, and method for reducing power consumption of analog-to-digital converter
US10079609B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2017 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Oct 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure discloses a DAC capacitor array, which includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.