Multiple silicon trenches forming method for MEMS sealing cap wafer and etching mask structure thereof
US10081541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2203/033
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed. The present invention can form a plurality of deep trenches with high aspect ratio on the MEMS sealing cap silicon substrate using conventional semiconductor processes, avoiding the problem that the conventional spin coating cannot be conducted on a sealing cap wafer with deep trenches using photoresist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.