Open loop solution in data buffer and RCD
US10082823B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.