Controller, bus circuit, control method, and recording medium
US10083138B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an instruction input to the target device and a response to the instruction input, predicting a response of the target device to the instruction acquired, and outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and a master circuit connected to the target device with the bus, the master circuit transmitting the instruction to the target device through the bus, and performing initial setting of the target device based on the fault report from the pseudo device circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.