Patent · US Active

Systems and methods for reducing power consumption of latch-based circuits

US10083267B1 · kind B1 · utility

1Cited by
0References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 4, 2016
Grant dateSep 25, 2018
Priority date—
Expiry dateNov 4, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/06
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.