Method and system providing mutli-level security to gate level information flow
US10083305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A preferred method for providing multi-level security to a gate level information flow receives or specifies a security lattice having more than two security levels. The security lattice defines how security levels relate to each other. A hardware design implementing information flows including flows having security levels specified by the security lattice is received. Logic is created for testing the hardware design in view of the security lattice. A logic function is created based upon the hardware design and the logic for testing to implement the security lattice. Another method receives a hardware design in a hardware description language. At least a portion of the hardware design is synthesized to gate level primitives. Functional component tracking logic supporting more than two-security levels is built from the gate level primitives. Functional components in the hardware design are simulated with the functional component tracking logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.