Isolation regions for semiconductor structures and methods of forming the same
US10083856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.