Methods of making multichannel devices with improved performance
US10084075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.