Low-inductance direct current power bus
US10084310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S903/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.