Five-level inverter and application circuit of the same
US10084392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Nov 4, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A five-level inverter and its application circuit are provided. The five-level inverter is enabled to output multiple levels of voltage by controlling different conduction combinations of first, second, third, fourth, fifth, sixth, seventh, and eighth switch transistors, as well as a clamping capacitor. Two conduction combinations may be selected for outputting a positive voltage, with currents flowing through the clamping capacitor in opposite directions in the two conduction combinations. Therefore the voltage of the clamping capacitor can be balanced by controlling the two conduction combinations. Similarly, when outputting a negative voltage, the voltage of the clamping capacitor can be balanced by controlling other two conduction combinations. Therefore, a balance of power capacitor voltage can be achieved at full power and full modulation without adding an extra hardware circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.