Patent · US Active

Top plate sampling circuit including input-dependent dual clock boost circuits

US10084466B1 · kind B1 · utility

2Cited by

1References

15Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Ani Xavier · Kanchinakote, IN
Neeraj Shrivastava · Bengaluru, IN
Arun Mohan · Bengaluru, IN

Key dates

Filing date	Dec 28, 2017
Grant date	Sep 25, 2018
Priority date	—
Expiry date	Dec 28, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C27/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.