Tester for integrated circuits on a silicon wafer and integrated circuit
US10088526B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3172
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A tester for integrated circuits on a silicon wafer includes an input/output connection for testing an integrated circuit. The tester comprises circuitry arranged for transferring a first data frame to the integrated circuit via the input/output connection, the first data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one test command and for receiving a second data frame via the input/output connection, the data in the second data frame received having a duration that is a multiple of the time reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.