Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency
US10088891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2014 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.