Systems and methods for bios update optimization
US10089105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory communicatively coupled to the processor, the memory having stored thereon a basic input/output system (BIOS) comprising a program of instructions executable by the processor for initializing one or more information handling resources of the information handling system during boot up or power on of the information handling system. The memory may comprise a plurality of firmware volumes comprising at least a first firmware volume having stored therein one or more components of the BIOS having a first expected update frequency and a second firmware volume having stored therein one or more components of the BIOS having a second expected update frequency less than that of the first expected update frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.