Queuing of decoding tasks according to priority in NAND flash controller
US10089175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.