Energy-efficient nonvolatile microprocessor
US10089182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An energy-efficient nonvolatile microprocessor includes a processing core, a nonvolatile flip-flop array, a set of nonvolatile interconnections, and a store-enable register. When a power source is recovered to a stable state, the processing core determines whether data of nonvolatile registers is not transmitted before power-off. If yes, the processing core executes programmable recovery entry decision to avoid recovery failures for different applications. The processing core has plural system states divided into programmer visible states and programmer invisible states. The nonvolatile interconnections are connected between the processing core and the nonvolatile flip-flop array. When the power source is unstable, the processing core only stores the programmer visible states into the nonvolatile flip-flop array and, at the same time, only stores the system states of the peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.