System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems
US10089194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.