Mode switching for increased off-chip bandwidth
US10089232B2 · kind B2 · utility
2Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a portion of allocated pins of a processor with switchable pins, connecting the processor to a memory interface configured to switch the switchable pins between a power mode and a signal mode, providing a metric configured to identify which of the power mode and the signal mode is most beneficial during 1 millisecond intervals, and switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.