Automated graphics and compute tile interleave
US10089775B2 · kind B2 · utility
0Cited by
8References
22Claims
0Family size
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Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system interleaves a combination of graphics renderer operations and compute shader operations. A set of API calls is analyzed to determine dependencies and identify candidates for interleaving. A compute shader is adapted to have a tiled access pattern. The interleaving is scheduled to reduce a requirement to access an external memory to perform reads and writes of intermediate data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.