Graphics processor logic for encoding increasing or decreasing values
US10089964B2 · kind B2 · utility
4Cited by
0References
15Claims
0Family size
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Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide for a graphics processing apparatus comprising a graphics processing unit including bounding volume logic to encode a first bounding volume and a second bounding volume for a bounding volume hierarchy, wherein the first bounding volume is to be encoded at a higher numerical precision relative to the second bounding volume and the first bounding volume encloses the second bounding volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.