Method for forming semiconductor structure having stress layers
US10090156B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Apr 3, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Apr 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.