Method for electrically aging a PMOS thin film transistor
US10090831B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 9, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0214
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.