Low power reset circuit
US10090833B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2472
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.