On-die termination circuit, a memory device including the on-die termination circuit, and a memory system including the memory device
US10090835B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Mar 22, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Mar 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor connected to the input buffer and at least one switching device configured to control a connection between the termination resistor and the input buffer. The switching device is turned on or off according to information about the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.