Over voltage tolerant circuit
US10090838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Sep 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an integrated circuit, which includes a processor core, a plurality of input/output (I/O) circuits, and a plurality of over voltage tolerant (OVT) circuits. Each I/O circuit is associated with an I/O pad and is associated with an OVT circuit of the plurality of OVT circuits. At least one of the OVT circuits includes a passive circuit, which is adapted to receive a pad voltage from the associated I/O pad; receive a supply voltage of the associated I/O circuit; and based on a relationship of the received pad voltage relative to the received supply voltage, selectively couple a gate of a transistor of the associated I/O circuit to the pad voltage to inhibit a leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.