Fraction-N digital PLL capable of canceling quantization noise from sigma-delta modulator
US10090845B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Mar 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/344
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.