Complete complementary code parallel offsets
US10090847B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method of converting an analog input signal to a digital output signal includes coupling an analog input signal to a plurality of analog-to-digital converters (ADCs) arranged in a parallel configuration. Pseudo-random discrete valued complementary offset voltage levels that span an input voltage range of the sum of the plurality of ADCs are generated. An amount of continuous, analog dither that randomly varies at values between the discrete offset voltage levels is generated, the analog dither being less than steps between the discrete offset voltage levels. On different clock cycles, different discrete offset voltage levels are coupled to at least some of the ADCs. At each ADC, the respectively coupled analog input, discrete offset voltage level, and continuous analog dither are quantized to obtain a digital output. The respective digital outputs are combined to obtain a linearized digital representation of the analog input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.