Patent · US Active

Decoding apparatus and decoding method including error correction process based on power differences

US10090967B2 · kind B2 · utility

0Cited by

4References

4Claims

0Family size

Assignee

MSTAR SEMICONDUCTOR, INC. · TW

Inventors

Yi-Ying Liao · Luodong, TW
Chen-Yi Liu · Xi'an, CN

Key dates

Filing date	Oct 5, 2016
Grant date	Oct 2, 2018
Priority date	—
Expiry date	Oct 5, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/2732
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A decoding apparatus includes an input power estimating circuit, an error correction decoder and a controller. The input power estimating circuit generates multiple estimated input powers for multiple sets of data included in a packet that needs to be corrected, and calculates respective power differences between the multiple estimated input powers and a reference power. The controller determines one or multiple candidate error positions according to one of the multiple power differences that is higher than a predetermined threshold. The error correction decoder performs a decoding process on the packet according to the one or multiple candidate error positions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.