Background reads to condition programmed semiconductor memory cells
US10095568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Apr 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.