Failover method, apparatus and system
US10095592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2016 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a second device, a transaction processing packet, where the transaction processing packet includes processing information about access of a host to a peripheral component interconnect express (PCIe) device, the processing information is used to describe information required for resuming a transaction when the transaction is interrupted, the second device further stores topology information of the PCIe device, and a driver for the PCIe device is loaded to the second device, and when detecting that the first device fails, continuing to process, by the second device according to the topology information, the driver, and the processing information, the transaction that is about the access of the host to the PCIe device and is being processed when a first device fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.