Computer based system for verifying layout of semiconductor device and layout verify method thereof
US10095825B2 · kind B2 · utility
1Cited by
58References
20Claims
0Family size
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Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | May 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.